Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) including semiconductor chips, thin film packages and printed circuit boards. ICs can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single semiconductor (e.g., Si) crystal substrate.
For complementary metal oxide semiconductor (CMOS) devices to be functional, the gates of each nFET and each pFET, which are typically comprised of polysilicon and a dielectric material having a dielectric constant greater than silicon dioxide (herein after “high k dielectric”), must be patterned without compromising the integrity of the gate material and the gate dielectric(s). For 15 nm node and beyond technologies, several device options are being contemplated, some of which entail the use of nano-channel devices to increase the carrier mobility and device performance, reduce the short channel effect, and to increase the scalability. The term “nano-channel” refers to a device whose channel diameter is on the order of about 50 nm or less.
Nano-channel devices typically, but not necessarily always, include nanowires (NWs) made of a semiconductor material including, for example, Si, SiGe, a III-V compound semiconductor, or a carbon nanotube (CNT) for use in the active channel area. Such nano-channels could be patterned with a conventional “top down” lithographic patterning technique or from a “bottom up” process with NW or CNT deposition atop a semiconductor substrate, e.g., Si, SiGe, a silicon-on-insulator (SOI) or a silicon germanium-on-insulator (SGOI) followed by conventional gate patterning such as those outlined in U.S. application Ser. No. 11/760,992, filed Jun. 11, 2007 and U.S. Patent Application Publication No. 2008/0045011-A1, publication date Feb. 21, 2008 or other prior art methodologies.
Irrespective of the employed methodology for fabricating the gate conductor, the use of a nano-channel material implies that conventional prior art plasma etching processes typically employed for patterning the latter will encounter some limitation during the etching process. This limitation entails difficulty in removing residue gate material that is beneath the nano-channel without compromising the integrity of the gate material as the isotropic etching process employed for removing the gate material will also etch some fraction of the gate conductor.
In view of the above, there is a need for providing a method of fabricating a nano-channel semiconductor device in which the patterning of the gate of the semiconductor device removes residue gate material beneath the nano-channel without compromising the integrity of the gate.